rev 2.1 ?2010 advanced linear devices, inc. 415 tasman drive, sunnyvale, ca 94089-1706 tel: (408) 747-1155 fax: (408) 747-1286 www.aldinc.com general description the ald1706a/ald1706b/ald1706/ald1706g is a monolithic cmos ultra micropower high slew-rate, high performance operational amplifier intended for a broad range of analog applications using 1v to 5v dual power supply systems, as well as +2v to +10v battery operated systems. all device characteristics are specified for +5v single supply or 2.5v dual supply systems. supply current is 40 a maximum at 5v supply voltage. it is manufactured with advanced linear devices' enhanced acmos silicon gate cmos process. the ald1706a/ald1706b/ald1706/ald1706g is designed to offer high performance for a wide range of applications requiring very low power dissipation. it has been developed specifically for the +5v single battery or 1v to 5v dual battery user and offers the popular industry standard single operational amplifier pin configuration. several important characteristics of the device make application easier to implement at those voltages. first, the operational amplifier can operate with rail to rail input and output voltages. this means the signal input voltage and output voltage can be close to or equal to the positive and negative supply voltages. this feature allows numerous analog serial stages and flexibility in input signal bias levels. second, the device was designed to accommodate mixed applications where digital and analog circuits may operate off the same power supply or battery. third, the output stage can typically drive up to 25pf capacitive and 20k ? resistive loads. these features, combined with extremely low input currents, high open loop voltage gain of 100v/mv, useful bandwidth of 400khz, a slew rate of 0.17v/ s, low offset voltage and temperature drift, make the ald1706a/ald1706b/ald1706/ald1706g a versatile, micropower operational amplifier. the ald1706a/ald1706b/ald1706/ald1706g, designed and fabricated with silicon gate cmos technology, offers 0.1 pa typical input bias current. on chip offset voltage trimming allows the device to be used without nulling in most applications. additionally, robust design and rigorous screening make this device especially suitable for operation in temperature-extreme environments and rugged conditions. features ? all parameters specified for +5v single supply or 2.5v dual supply systems ? rail to rail input and output voltage ranges ? no frequency compensation required -- unity gain stable ? extremely low input bias currents -- 1.0pa typical (30pa max.) ? ideal for high source impedance applications ? dual power supply 1.0v to 5.0v operation ? single power supply +2.0v to +10.0v operation ? high voltage gain -- typically 100v/mv @ 2.5v(100db) ? drive as low as 10k ? load ? output short circuit protected ? unity gain bandwidth of 0.7mhz ? slew rate of 0.7v/ s ? low power dissipation ? suitable for rugged, temperature-extreme environments ultra micropower rail-to-rail cmos operational amplifier ald1706a/ald1706b ald1706/ald1706g a dvanced l inear d evices, i nc. applications ? voltage amplifier ? voltage follower/buffer ? charge integrator ? photodiode amplifier ? data acquisition systems ? high performance portable instruments ? signal conditioning circuits ? sensor and transducer amplifiers ? low leakage amplifiers ? active filters ? sample/hold amplifier ? picoammeter ? current to voltage converter operating temperature range 0 c to +70 c0 c to +70 c -55 c to 125 c 8-pin 8-pin 8-pin small outline plastic dip cerdip package (soic) package package ald1706asal ald1706apal ald1706ada ald1706bsal ald1706bpal ALD1706BDA ald1706sal ald1706pal ald1706da ald1706gsal ald1706gpal * contact factory for leaded (non-rohs) or high temperature versions. ordering information (?l? suffix denotes lead-free (rohs)) pin configuration * n/c pins are internally connected. do not connect externally. 1 2 2 3 4 8 7 6 5 n/c -in +in n/c out n/c v - v + top view sal, pal, da packages
ald1706a/ald1706b advanced linear devices 2 of 9 ald1706/ald1706g absolute maximum ratings supply voltage, v + 10.6v differential input voltage range -0.3v to v + +0.3v power dissipation 600 mw operating temperature range sal, pal packages 0 c to +70 c da package -55 c to +125 c storage temperature range -65 c to +150 c lead temperature, 10 seconds +260 c caution: esd sensitive device. use static control procedures in esd controlled environment. operating electrical characteristics t a = 25 c v s = 2.5v unless otherwise specified 1706a 1706b 1706 1706g test parameter symbol min typ max min typ max min typ max min typ max unit conditions supply v s 1.0 5.0 1.0 5.0 1.0 5.0 1.0 5.0 v dual supply voltage v + 2.0 10.0 2.0 10.0 2.0 10.0 2.0 10.0 v single supply input offset v os 0.9 2.0 4.5 10.0 mv r s 100k ? voltage 1.7 2.8 5.3 11.0 mv 0 c t a +70 c input offset i os 0.1 25 0.1 25 0.1 25 0.1 30 pa t a = 25 c current 240 240 240 450 pa 0 c t a +70 c input bias i b 0.1 30 0.1 30 0.1 30 0.1 50 pa t a = 25 c current 300 300 300 600 pa 0 c t a +70 c input voltage v ir -0.3 5.3 -0.3 5.3 -0.3 5.3 -0.3 5.3 v v + = +5v range -2.8 2.8 -2.8 2.8 -2.8 2.8 -2.8 2.8 v v s = 2.5v input resistance r in 10 12 10 12 10 12 10 12 ? input offset voltage drift tcv os 77 710 v/ cr s 100k ? power supply psrr 70 80 65 80 65 80 60 80 db r s 100k ? rejection ratio 70 80 65 80 65 80 60 80 db 0 c t a +70 c common mode cmrr 70 83 65 83 65 83 60 83 db r s 100k ? rejection ratio 70 83 65 83 65 83 60 83 db 0 c t a +70 c large signal a v 32 100 32 100 32 100 20 80 v/ mv r l = 1m ? voltage gain 20 20 20 10 v/ mv r l = 1m ? 0 c t a +70 c output v o low 0.001 0.01 0.001 0.01 0.001 0.01 0.001 0.01 v r l =1m ? voltage v o high 4.99 4.999 4.99 4.999 4.99 4.999 4.99 4.999 v 0 c t a +70 c range v o low -2.40 -2.30 -2.40 -2.30 -2.40 -2.30 -2.40 -2.30 v r l =100k ? v o high 2.30 2.40 2.30 2.40 2.30 2.40 2.30 2.40 v 0 c t a +70 c output short circuit current i sc 200 200 200 200 a supply current i s 20 40 20 40 20 40 20 50 av in = 0v no load power dissipation p d 200 200 200 250 wv s = 2.5v
ald1706a/ald1706b advanced linear devices 3 of 9 ald1706/ald1706g 1706bda 1706da test parameter symbol min typ max min typ max unit conditions v s = 2.5v -55 c t a +125 c unless otherwise specified input offset v os 3.0 6.5 mv r s 100k ? voltage input offset i os 8.0 8.0 na current input bias i b 10.0 10.0 na current power supply psrr 60 75 60 75 db r s 1m ? rejection ratio common mode cmrr 60 83 60 83 db r s 1m ? rejection ratio large signal a v 15 50 15 50 v/ mv r l = 1m ? voltage gain output voltage v o low -2.40 -2.30 -2.40 -2.30 v range v o high 2.30 2.40 2.30 2.40 v r l = 1m ? input capacitance c in 11 11pf bandwidth b w 400 400 400 400 khz slew rate s r 0.17 0.17 0.17 0.17 v/ sa v = +1 r l = 1m ? rise time t r 1.0 1.0 1.0 1.0 sr l = 1m ? overshoot 20 20 20 20 % r l =1m ? factor c l = 25pf settling time t s 10.0 10.0 10.0 10.0 s 0.1% a v = -r l =1m ? c l = 25pf t a = 25 c v s = 2.5v unless otherwise specified 1706a 1706b 1706 1706g test parameter symbol min typ max min typ max min typ max min typ max unit conditions power supply psrr 70 70 70 70 db r s 1m ? rejection ratio common mode cmrr 70 70 70 70 db r s 1m ? rejection ratio large signal a v 50 50 50 50 v/ mv r l =1m ? voltage gain output voltage v o low -0.95 -0.9 -0.95 -0.9 -0.95 -0.9 -0.95 -0.9 v r l =1m ? range v o high 0.9 0.95 0.9 0.95 0.9 0.95 0.9 0.95 v bandwidth b w 0.3 0.3 0.3 0.3 mhz slew rate s r 0.17 0.17 0.17 0.17 v/ sa v = +1 c l = 25pf t a = 25 c v s = 1.0v unless otherwise specified 1706a 1706b 1706 1706g test parameter symbol min typ max min typ max min typ max min typ max unit conditions operating electrical characteristics (cont'd)
ald1706a/ald1706b advanced linear devices 4 of 9 ald1706/ald1706g design & operating notes: 1. the ald1706a/ald1706b/ald1706/ald1706g cmos operational amplifier uses a 3 gain stage architecture and an improved frequency compensation scheme to achieve large voltage gain, high output driving capability, and better frequency stability. in a conventional cmos operational amplifier design, compensation is achieved with a pole splitting capacitor together with a nulling resistor. this method is, however, very bias dependent and thus cannot accommodate the large range of supply voltage operation as is required from a stand alone cmos operational amplifier. the ald1706a/ald1706b/ald1706/ald1706g is internally compensated for unity gain stability using a novel scheme that does not use a nulling resistor. this scheme produces a clean single pole roll off in the gain characteristics while providing for more than 70 degrees of phase margin at the unity gain frequency. 2. the ald1706a/ald1706b/ald1706/ald1706g has complementary p-channel and n-channel input differential stages connected in parallel to accomplish rail-to-rail input common mode voltage range. this means that with the ranges of common mode input voltage close to the power supplies, one of the two differential stages is switched off internally. to maintain compatibility with other operational amplifiers, this switching point has been selected to be about 1.5v below the positive supply voltage. since offset voltage trimming on the ald1706a/ald1706b/ald1706/ald1706g is made when the input voltage is symmetrical to the supply voltages, this internal switching does not affect a large variety of applications such as an inverting amplifier or non-inverting amplifier with a gain larger than 2.5 (5v operation), where the common mode voltage does not make excursions above this switching point. the user should however, be aware that this switching does take place if the operational amplifier is connected as a unity gain buffer and should make provision in his design to allow for input offset voltage variations. 3. the input bias and offset currents are essentially input protection diode reverse bias leakage currents, and are typically less than 1pa at room temperature. this low input bias current assures that the analog signal from the source will not be distorted by input bias currents. normally, this extremely high input impedance of greater than 10 12 ? would not be a problem as the source impedance would limit the node impedance. however, for applications where source impedance is very high, it may be necessary to limit noise and hum pickup through proper shielding. 4. the output stage consists of class ab complementary output drivers, capable of driving a low resistance load. the output voltage swing is limited by the drain to source on-resistance of the output transistors as determined by the bias circuitry, and the value of the load resistor. when connected in the voltage follower configuration, the oscillation resistant feature, combined with the rail to rail input and output feature, makes an effective analog signal buffer for medium to high source impedance sensors, transducers, and other circuit networks. 5. the ald1706a/ald1706b/ald1706/ald1706g operational amplifier has been designed to provide full static discharge protection. internally, the design has been carefully implemented to minimize latch up. however, care must be exercised when handling the device to avoid strong static fields that may degrade a diode junction, causing increased input leakage currents. in using the operational amplifier, the user is advised to power up the circuit before, or simultaneously with, any input voltages applied and to limit input voltages to not exceed 0.3v of the power supply voltage levels. 6. the ald1706a/ald1706b/ald1706/ald1706g , with its micropower operation, offers numerous benefits in reduced power supply requirements, less noise coupling and current spikes, less thermally induced drift, better overall reliability due to lower self heating, and lower input bias current. it requires practically no warm up time as the chip junction heats less than 0.1 c above ambient temperature under most operating conditions. typical performance characteristics input bias current as a function of ambient temperature ambient temperature ( c) 1000 100 10 0.1 1.0 input bias current (pa) 100 -25 0 75 125 50 25 -50 10000 v s = 2.5v open loop voltage gain as afunction of load resistance 10m load resistance ( ? ) 10k 100k 1m 1000 100 10 1 open loop voltage gain (v/mv) v s = 2.5v t a = 25 c common mode input voltage range as a function of supply voltage supply voltage (v) common mode input voltage range (v) 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 t a = 25 c supply current as a function of supply voltage supply voltage (v) 80 40 60 0 20 supply current ( a) 0 1 2 3 4 5 6 t a = -55 c +25 c +70 c +125 c inputs grounded output unloaded -25 c
ald1706a/ald1706b advanced linear devices 5 of 9 ald1706/ald1706g typical performance characteristics (cont'd) input offset voltage as a function of ambient temperature representative units ambient temperature ( c) input offset voltage (mv) -50 -25 0 +25 +50 +75 +100 +125 +4 +5 +3 +1 +2 0 -2 -1 -4 -3 -5 v s = 2.5v input offset voltage as a function of common mode input voltage common mode input voltage (v) -2 -1 0 +1 +3 +2 15 10 5 -5 -10 0 -15 input offset voltage (mv) v s = 2.5v t a = 25 c small - signal transient response 100mv/div 50mv/div 10 s/div v s = 2.5v t a = 25 c r l = 100k ? c l = 25pf large - signal transient response v s = 1.0v t a = 25 c r l = 100k ? c l = 25pf 2v/div 500mv/div 10 s/div large - signal transient response 2v/div 10 s/div 5v/div v s = 2.5v t a = 25 c r l = 100k ? c l = 25pf open loop voltage gain as a function of frequency frequency (hz) 1 10 100 1k 10k 1m 10m 100k 120 100 80 60 40 20 0 -20 open loop voltage gain (db) v s = 2.5v t a = 25 c 90 0 45 180 135 phase shift in degrees open loop voltage gain as a function of supply voltage and temperature supply voltage (v) 1000 100 10 1 open loop voltage gain (v/mv) 0 2 4 6 8 -55 c t a +125 c r l = 100k ? output voltage swing as a function of supply voltage supply voltage (v) 0 1 2 3 4 7 6 5 6 5 4 3 2 1 output voltage swing (v) -55 c t a +125 c r l = 100k ?
ald1706a/ald1706b advanced linear devices 6 of 9 ald1706/ald1706g typical applications rail-to-rail voltage follower/buffer charge integrator + 1000pf +2.5v -2.5v 1m v out v in high input impedance rail-to-rail precision dc summing amplifier rail-to-rail voltage comparator high impedance non-inverting amplifier photo detector current to voltage converter + +1v -1v 900k 100k v out v in + - +2.5v -2.5v r f = 5m i photodiode v out = 1 x r f r l = 100k wien bridge oscillator micropower buffered variable voltage source + +1.0v -1.0v 250k 0.0015 f 100k 0.0015 f c 100k r c power supply = 1.0 v r v out = sinewave 2v peak to peak 1 2 r c 1.0khz f v out + 2m v + v + 2.0v v + 12.0v 0.1 v out (v + - 0.1) v ouput current 200 a 1 f v out v in - + output 50k 0.1 f +5v 10m +5v v in 0 v in v + v- = - 2.5v 10m 10m 10m 10m 10m 10m r in = 10m ? accuracy limited by resistor tolerances and input offset voltage v+ = +2.5v - + 0.1 f 0.1 f v out v- v out v+ v 1 v 4 v 3 v 2 v out = v 1 + v 2 - v 3 - v 4 - + output 5v 0.1 f 0 v in 5v v in z in = 10 12 ? ~ * see rail to rail waveform
ald1706a/ald1706b advanced linear devices 7 of 9 ald1706/ald1706g 8 pin plastic soic package soic-8 package drawing millimeters inches min max min max dim a a 1 b c d-8 e e h l s 1.75 0.25 0.45 0.25 5.00 4.05 6.30 0.937 8 0.50 0.053 0.004 0.014 0.007 0.185 0.140 0.224 0.024 0 0.010 0.069 0.010 0.018 0.010 0.196 0.160 0.248 0.037 8 0.020 1.27 bsc 0.050 bsc 1.35 0.10 0.35 0.18 4.69 3.50 5.70 0.60 0 0.25 ? l c h s (45 ) ? e a a 1 b d s (45 ) e
ald1706a/ald1706b advanced linear devices 8 of 9 ald1706/ald1706g 8 pin plastic dip package pdip-8 package drawing b 1 s b e e 1 d e a 2 a 1 a l c e 1 ? millimeters inches min max min max dim a a 1 a 2 b b 1 c d-8 e e 1 e e 1 l s-8 ? 3.81 0.38 1.27 0.89 0.38 0.20 9.40 5.59 7.62 2.29 7.37 2.79 1.02 0 5.08 1.27 2.03 1.65 0.51 0.30 11.68 7.11 8.26 2.79 7.87 3.81 2.03 15 0.105 0.015 0.050 0.035 0.015 0.008 0.370 0.220 0.300 0.090 0.290 0.110 0.040 0 0.200 0.050 0.080 0.065 0.020 0.012 0.460 0.280 0.325 0.110 0.310 0.150 0.080 15
ald1706a/ald1706b advanced linear devices 9 of 9 ald1706/ald1706g 8 pin cerdip package cerdip-8 package drawing a a 1 b b 1 c d-8 e e 1 e e 1 l l 1 l 2 s ? 3.55 1.27 0.97 0.36 0.20 -- 5.59 7.73 3.81 3.18 0.38 -- 0 5.08 2.16 1.65 0.58 0.38 10.29 7.87 8.26 5.08 -- 1.78 2.49 15 millimeters inches min max min max dim 0.140 0.050 0.038 0.014 0.008 -- 0.220 0.290 0.150 0.125 0.015 -- 0 0.200 0.085 0.065 0.023 0.015 0.405 0.310 0.325 0.200 -- 0.070 0.098 15 2.54 bsc 7.62 bsc 0.100 bsc 0.300 bsc e e 1 c e 1 ? s b l d b 1 e a l 2 a 1 l 1
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